AI compute evaluation and deployment platform for EU infrastructure

Scope: Proposals innovations should address one or more of the several domains : WBG substrates to reduce EU dependency on material and provide more sustainable, industrially compatible solutions. WBG platform for cost effectiveness, available in 300mm for GaN and/or SiC to improve yield and power density and close gaps in the value chain. A toolbox (e.g. wafer cut, smart stacking, thin layer transfer, epitaxy, UWBG materials) for further innovation schemes. Next generation or optimised new power semiconductor devices fitting their application. Adding intelligence to power semiconductor devices on control and/or sensor side. Facilitate the propagation of EU Packaging/Integration excellence along the entire value chain e.g. pre-packages or power semiconductor device packaging solutions to enable power device/system integration and strengthen Europe’s competitiveness in advanced packaging. Explore the use of heterogeneous and functional integration for improved performance, reliability, robustness and cost competitiveness. Rising operative voltage, frequency, current and thermal features that are common challenge on power electronics across the different application sectors. Provide…

Expected Impact: Projects funded under this call are expected to deliver tangible industrial outputs that demonstrably advance the readiness and affordability of future governmental Ka-band user terminals for IRIS2 and GOVSATCOM services. Expected outputs include, for example: qualified production processes, calibrated sub-assemblies, pilot-run units, validated manufacturing equipment chains or manufacturing cost models. Purely analytical deliverables (studies, design reports) are not sufficient as primary outputs but may complement the above. Where relevant, outputs shall include documented design assumptions, interface parameters or process specifications enabling adaptation to different terminal configurations with limited re-engineering, so as to support uptake in follow-on integration, pilot deployment and scale-up activities. Objective: The aim of this call for proposals is to advance the industrial readiness of European Ka-band user terminal technologies, subsystems and manufacturing processes, with a view to enabling cost-effective production of user terminals for services provided under the Union secure connectivity programme (IRIS²) and GOVSATCOM. The target reference…

Expected Outcome: The targeted outcomes reflect the above challenges and cover a comprehensive Front End module design which: Covers the FR3 range as defined by the relevant Agenda Item of WRC 27 (7 to 15 GHz range) with possible extension up to 24 GHz if required by some regional implementations, with inherent tuning capabilities to accommodate potential regional variations. Mitigates interferences with incumbent FR3 band users and maximises sharing capabilities across the band in line with the European regulatory approach on spectrum sharing. Enables integration of a large number of antenna elements beyond the State of the Art and support massive MIMO implementation with compensation of increased path loss compared to 5G FR1 implementations. Enables at least an order-of-magnitude increase in RF processing compared to 5G FR1 implementations. Enables 5G cell site reuse and minimises deployment complexity on top of 5G sites deployment. Enables low-cost and low energy implementation of the elementary constituent modules, efficient packaging and is mainly based on the integration of microelectronics heterogeneous technologies where European industry has strong expertise and…

Expected Outcome: Objectives and profile of the ERC Plus Grant Principal Investigator The ERC Plus Grant supports outstanding Principal Investigators who address a major scientific challenge. Applications for ERC Plus Grants should be for projects that could not be carried out with a regular ERC grant. Applicants should explain how the proposed project aims go beyond those of a regular ERC project, for example, because they have a vision to transform their field or open a new field of research. Scholars at all career stages can apply for an ERC Plus Grant if they have an outstanding record of scientific achievement at the forefront of their field. Their intellectual leadership will be evaluated in comparison to peers at their own career stage. It is expected that a researcher may be the Principal Investigator of only one ERC Plus Grant in their lifetime. Applicants should be aware that every year, only some 30 ERC Plus Grants can be awarded across all fields and all career stages, compared to approximately 1000 Starting, Consolidator and Advanced Grants. This level of competitiveness should be taken into account when considering whether to submit an application. Size of ERC Plus…

Expected Outcome: Expected outcomes: A sustained pipeline of highly qualified semiconductor graduates, with shorter time-to-readiness for industry roles; greater inflow of diverse talent including women and underrepresented groups; improved intra- and extra-EU student mobility; and strong complementarity with existing Chips Act infrastructure such as pilot lines, design platforms, and Competence Centres. Scope: This call funds the creation of specialised academic "Hubs of Excellence" in critical semiconductor technology areas (e.g. chip design, manufacturing, photonics, power electronics). Projects should build industry-aligned Bachelor, Master, and PhD programmes.

Expected Outcome: The focus needs to be on areas where Digital Partnership countries bring strong complementary expertise, including advanced packaging, heterogeneous integration, and photonic chip technologies. The topic would aim to foster collaboration between European and Digital Partnership countries’ R&I communities. Projects are expected to contribute to the following outcomes: • Innovative design and integration concepts for neuromorphic computing systems supporting very low energy consumption, connectivity, embedded functions for mobile applications. • Alternative manufacturing process technologies for semiconductor chips including frontend or backend for heterogenous integration. The technologies should sustain in the mid- and long-term the fast-paced evolution of device performance, miniaturisation and cost, while reducing the environmental footprint. • Very advanced packaging solutions aiming heterogeneous integration of multiple functions and materials for applications in communication (RF, mmW or THz), sensing, actuating, power management and active/passive integration.